Search - verilog RAM

[Other resource] verilog_YUYAN

Description: verilog语言写的同步双端口设计文件!!!是一个不错的双口RAM的设计文件！
Platform: | Size: 50259 | Author: JP | Hits:

[Software Engineering] the_ram_of_fPga

Description: 基于FPGA的SDRM设计，VERILOG语言写的同步双端口设计文件!!!是一个不错的双口RAM的设计文件！
Platform: | Size: 8804 | Author: JP | Hits:

[Other] ram_sp_sr_sw

Description: Synchronous read write RAM verilog
Platform: | Size: 965 | Author: 李明 | Hits:

[Other resource] an_dcfifo_top_restored

Description: alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM 实现高速到低速时钟域的数据传输，值得学习。
Platform: | Size: 928622 | Author: alison | Hits:

[Other] proposal

Description: 某个著名博士关于如何查找文献，和学术论文发表的ppt-a famous literature on how to identify and academic papers published ppt
Platform: | Size: 35840 | Author: 张华 | Hits:

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

Description: 可以用的通用SDRAM控制器,可以用在FPGA上,是SDR类型的-Can use the generic SDRAM controller can be used in the FPGA, the SDR is the type of
Platform: | Size: 9216 | Author: 郑宏超 | Hits:

[SCM] ProfiBus_Modbus_2008

Description: SPC3 PROGRAMS SP C3 PROGRAMS
Platform: | Size: 5120 | Author: ZHUWEIBING | Hits:

[VHDL-FPGA-Verilog] InvMod_test

Description: verilog实现的1024位的大数模逆算法，引入RAM作为数据通道-verilog to achieve the 1024 Modular inverse algorithms, the introduction of RAM as a data channel
Platform: | Size: 5120 | Author: 李丹 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] ZBTSRAM

Description: 高速同步SRAM控制器参考设计VHDL代码-High-speed synchronous SRAM controller reference design VHDL code
Platform: | Size: 8192 | Author: wang | Hits:

[VHDL-FPGA-Verilog] fifo_test

Description: FIFO读写verilog程序，经本人验证，能够顺利运行。实现FPGA对fifo的控制。-the example of writing and reading the fifo ram of the fpag,i have already tested it.
Platform: | Size: 2048 | Author: saul | Hits:

[VHDL-FPGA-Verilog] in_out_put

Description: 双向RAM的Verilog程序，能实现双向传数据-The Verilog bidirectional RAM process, to achieve a two-way mass data
Platform: | Size: 749568 | Author: you | Hits:

[Other] ddpi_tx

Description: verilog语言编写的一个接口文件，使用乒乓ram-verilog language of an interface file, use the ping-pong ram
Platform: | Size: 1024 | Author: yaop | Hits:

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[Other resource] verilog_YUYAN

[Software Engineering] the_ram_of_fPga

[Other] ram_sp_sr_sw

[Other resource] an_dcfifo_top_restored

[Other] proposal

[VHDL-FPGA-Verilog] SDR_SDRAM_controler_verilog

[SCM] ProfiBus_Modbus_2008

[VHDL-FPGA-Verilog] InvMod_test

[VHDL-FPGA-Verilog] DW8051_ALL

[VHDL-FPGA-Verilog] ZBTSRAM

[VHDL-FPGA-Verilog] fifo_test

[VHDL-FPGA-Verilog] in_out_put

[Other] ddpi_tx

[VHDL-FPGA-Verilog] 61EDA_H182

[Embeded-SCM Develop] ramtest

[VHDL-FPGA-Verilog] 256fft

[VHDL-FPGA-Verilog] DualPortRAM

[VHDL-FPGA-Verilog] dp_ram

[VHDL-FPGA-Verilog] idt71v416s10

[VHDL-FPGA-Verilog] LIP2321CORE_cpu_local_ram

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